Divisor Latch Low Register
| DLL | Divisor Latch Low Field The output baud rate is equal to the serial clock (SCLK) frequency divided by 16 times the value of the baud rate divisor, as follows: baud rate = (SCLK) / (16 x divisor). Note: With the Divisor Latch registers (UART_DLL and UART_DLH) set to 0, the baud clock is disabled and no serial communication will occur. Also, once the DLL is set, at least 8 clock cycles of the slowest UART clock should be allowed to pass before transmitting or receiving data. |